With the constant increase in digital circuit complexity, multiple levels of abstraction in circuit representation are typically needed. Gate level and switch level representations are two other forms of circuit representations that are commonly used in simulation of the operation of integrated circuits. A gate level representation can be used to provide a schematic description of circuit components as interconnections of basic blocks having known Boolean functionalities. A switch level representation provides a representation of switches (transistors) and gates that implement the desired functionality for a particular circuit. For an integrated circuit to meet strict operating criteria in terms of speed, power, and surface area, it is generally necessary to create custom designs at the switch level. However, traditional techniques for verifying such designs are generally expensive and can incur errors.
Static timing analysis (STA) is one of the most popular methods for verifying the timing of synchronous circuits in an integrated circuit. To conduct a static timing analysis, it is necessary to provide a set of timing arcs with appropriate side input sensitizations. For doing static timing analysis, a set of timing arcs with appropriate side input sensitizations are needed. The timing arcs need to be generated automatically using MOS switch modeling and Boolean algebra. This can be accomplished by determining the pull-up and pull-down logic functions for the circuit output nets.
BDD based boolean algebra is used to determine the pull-up and pull-down functions. Each variable in the function is associated with a state. The state (on a net) can be one of the following: 1) previous, 2) present, or 3) next.
The function solve model for solving the output net pull-up and pull-down function assumes similar strength of devices. This results in cases where a pull-up path and a simultaneous pull-down path are assumed to lead to a contention. In case of dynamic circuits, however, this is not true. The feedback path devices are sized smaller than the devices in the feed-forward path. Therefore, the contention sensitizations need to be resolved to a logic value. Moreover, there is a need to remove the contention and undriven sensitizations from the net output by resolving the contention and undriven sensitizations.